1. Field of the Invention
The present invention relates to a double-balanced modulator and a quadri-phase shift keying device using the double-balanced modulator.
2. Related Background Art
A conventional quadri-phase shift keying device (QPSK) used in the field of the digital communication will be described with reference to FIG. 4.
The quadri-phase shift keying device is constructed by a first double-balanced modulator 101 and a second double-balanced modulator 131. The first double-balanced modulator 101 is constructed by a first pair of preamplifiers 104 for amplifying first balance signals supplied to a first pair of input terminals 102 and 103 and first and second differential amplifiers 105 and 106 for further amplifying the signals amplified by the first pair of preamplifiers 104.
Similarly, the second double-balanced modulator 131 is constructed by a second pair of preamplifiers 134 for amplifying second balance signals supplied to a second pair of input terminals 132 and 133 and third and fourth differential amplifiers 135 and 136 for further amplifying the signals amplified by the second pair of preamplifiers 134.
The first pair of preamplifiers 104 in the first double-balanced modulator 101 has first and second transistors 107 and 108. Constant current sources 109 and 110 are provided for the emitters of the transistors 107 and 108. The one input terminal 102 and the base of the first transistor 107 are connected. The other input terminal 103 and the base of the second transistor 108 are connected.
The first differential amplifier 105 is constructed by third and fourth transistors 116 and 117 whose emitters are connected to each other. The emitters are also connected to the collector of the first transistor 107. The second differential amplifier 106 is similarly constructed by fifth and sixth transistors 118 and 119 whose emitters are connected to each other. The emitters are also connected to the collector of the second transistor 108. The base of the third transistor 116 and the base of the sixth transistor 119 are connected to each other. The base of the fourth transistor 117 and the base of the fifth transistor 118 are connected to each other. A first balance carrier signal is supplied across the bases.
An output of the first differential amplifier 105 and an output of the second differential amplifier 106 are supplied to a first adder 120. The first adder 120 has: a first load resistor 121 which is commonly used by the collector of the third transistor 116 that is one of the transistors constructing the first differential amplifier 105 and the collector of the fifth transistor 118 that is one of the transistors constructing the second differential amplifier 106; and a second load resistor 122 which is commonly used by the collector of the fourth transistor 117 that is the other one of transistors constructing the first differential amplifier 105 and the collector of the sixth transistor 119 that is the other one of the transistors constructing the second differential amplifier 106. Consequently, a first double-balanced differential amplifier 123 is constructed by the first differential amplifier 105, the second differential amplifier 106, and the first adder 120. A modulated signal (first modulated signal) is generated between the collectors of the third and fifth transistors 116 and 118 and the collectors of the fourth and sixth transistors 117 and 119 which are connected to each other.
On the other hand, the second pair of preamplifiers 134 in the second double-balanced modulator 131 has seventh and eighth transistors 137 and 138. Constant current sources 139 and 140 are provided for the emitters of the transistors 137 and 138, respectively. The one input terminal 132 and the base of the seventh transistor 137 are connected. The other input terminal 133 and the base of the eighth transistor 138 are connected.
The third differential amplifier 135 is constructed by ninth and tenth transistors 146 and 147 whose emitters are connected to each other. The emitters are also connected to the collector of the seventh transistor 137. The fourth differential amplifier 136 is similarly constructed by eleventh and twelfth transistors 148 and 149 whose emitters are connected to each other. The emitters are connected to the collector of the eighth transistor 138. The base of the ninth transistor 146 and the base of the twelfth transistor 149 are connected to each other, the base of the tenth transistor 147 and the base of the eleventh transistor 148 are connected to each other. A second balance carrier signal having the phase different from that of the first balance carrier signal by 90.degree. is inputted across the bases.
An output of the third differential amplifier 135 and an output of the fourth differential amplifier 136 are inputted to a second adder 150. The second adder 150 has: a third load resistor 151 which is commonly used by the collector of the ninth transistor 146 that is one of the transistors constructing the third differential amplifier 135 and the collector of the eleventh transistor 148 that is one of the transistors constructing the fourth differential amplifier 136; and a fourth load resistor 152 commonly used by the collector of the tenth transistor 147 that is the other one of the transistors constructing the third differential amplifier 135 and the collector of the twelfth transistor 149 that is the other one of the transistors constructing the fourth differential amplifier 136. Consequently, a second double-balanced differential amplifier 153 is constructed by the third differential amplifier 135, the fourth differential amplifier 136, and the second adder 150. A modulated signal (second modulated sinal) is generated between the collectors of the ninth and eleventh transistors 146 and 148 and the collectors of the tenth and twelfth transistors 147 and 149 which are connected to each other.
The first balance carrier signal which is inputted to the first double-balanced differential amplifier 123 and the second balance carrier signal which is inputted to the second double-balanced differential amplifier 153 are generated from a balance carrier signal CW from a carrier oscillator (not shown) by a phase shifter 154.
The first and second modulated signals are synthesized and the synthesized signal is generated as a modulated signal generated by the quadri-phase shift keying device.
In the conventional quadri-phase shift keying device, the base of the first transistor 107 and the base of the second transistor 108 which construct the first pair of preamplifiers 104 are directly coupled to the first pair of input terminals 102 and 103, respectively. Consequently, when a buffer amplifier at the front stage for supplying the first balance signal to the first pair of input terminals 102 and 103 is directly connected to the pair of input terminals 102 and 103, the base voltages of the first and second transistors 107 and 108 depend on the bias current of the buffer amplifier. If the bias current is not in a balanced state, therefore, a difference occurs between the base voltage of the first transistor 107 and the base voltage of the second transistor 108 and the balance of the first double-balanced modulator 101 is lost. The first balance carrier signal is consequently leaked from the first adder 120 and is inputted to a circuit connected at the post stage, thereby causing generation of a disturbance signal.
Similarly, the base of the seventh transistor 137 and the base of the eighth transistor 138 which construct the second pair of preamplifiers 134 are directly connected to the second pair of input terminals 132 and 133. Consequently, when a buffer amplifier at the front stage for supplying the first balance signal to the second pair of input terminals 132 and 133 is directly connected to the pair of input terminals 132 and 133, the base voltages of the seventh and eighth transistors 137 and 138 depend on the bias current of the buffer amplifier. If the bias current is not in a balanced state, therefore, a difference occurs between the base voltage of the seventh transistor 137 and the base voltage of the eighth transistor 138, and the balance of the second double-balanced modulator 131 is lost. The second balance carrier signal is therefore leaked from the second adder 150 and is inputted to a circuit connected at the post stage, thereby causing generation of a disturbance signal.
The conventional quadri-phase shift keying device has a problem such that when the balanced state between the first double-balanced modulator 101 and the second double-balanced modulator 131 is lost, the leak of the balance carrier increases.